This application claims the benefit of Korean Patent Application No. 2001-9340, filed on Feb. 23, 2001, under 35 U.S.C. xc2xa7119, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a data read method of the semiconductor memory device.
2. Description of Related Art
In a typical semiconductor memory device, different memory cells have different path lengths to a current sense amplifier. The different path lengths result in a difference of the speed of reading. At its worst, the difference is the largest between data read from memory cell farthest from the current sense amplifier and data read from the memory cell nearest to the current sense amplifier.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device. The semiconductor memory device includes a plurality of memory cell arrays 10-1 to 10-8. Each of the memory cell arrays 10-1 to 10-8 includes a plurality of memory cells MC1 and MC1B to MC4 and MC4B near a crossing point of a plurality of word lines WL1 to WLm and a plurality of bit line pairs BL1P to BL4P.
The bit line pairs BL1P to BL4P are connected to sense amplifiers 12-1 to 12-4, data IO gates IOG1 to IOG4, bit line isolation gates ISG1 to ISG4, and pre-charge circuits PRE1 to PRE4, respectively.
Each of the data IO gates IOG1 to IOG4 includes NMOS transistors N1 and N2. Each of the bit line isolation gates ISG1 to ISG4 includes NMOS transistors N3 and N4. Each of the pre-charge circuits PRE1 to PRE4 includes NMOS transistors N5 and N6.
A column decoder 18 decodes a column address CA to generate column selecting signals Y0 to Yn.
Each of local data IO line pairs LIO1P to LIO8P is arranged between the two adjacent memory cell array blocks, and current sense amplifier load circuits 14-1 to 14-9 are connected to the local data IO line pairs LIO1P to LIO8P, respectively.
The local data IO line pairs LIO12P and LIO78P are line pairs shared between the adjacent two memory cell array blocks. The local data IO line pairs LIO1P and LIO78P are connected to a data IO line pair DIO1P, and the local data IO line pairs LIO12P and LIO8P are connected to a data IO line pair DIO2P. The data IO line pairs DIO1P and DIO2P are connected to the current sense amplifiers 16-1 and 16-2, respectively.
Of all the cells in the array, FIG. 1 only shows the memory cells MC1 and MC1B, and MC2 and MC2B that are the farthest from the current sense amplifier 16-1 and 16-2, and also the memory cells MC3 and MC3B, and MC4 and MC4B that are the nearest to the current sense amplifier 16-1 and 16-2. It also shows a circuit configuration to input into and output from the memory cells MC1 and MC1B to MC4 and MC4B.
In FIG. 1, xe2x80x9cSAxe2x80x9d denotes a bit line sense amplifier, xe2x80x9cCSALxe2x80x9d denotes a current sense amplifier load circuit, and xe2x80x9cCSAxe2x80x9d denotes a current sense amplifier.
A read operation of the semiconductor memory device of FIG. 1 is as follows: a pre-charge signal PRE is applied to pre-charge the bit line pairs BL1P to BL4P. An active command and a row address (not shown) are applied, so that the word line WL1 is enabled. When a bit line isolation signal ISO1 having a logic xe2x80x9chighxe2x80x9d level is generated, a data transmission is performed between the memory cells MC1 and MC1B, and MC2 and MC2B that are connected to the word line WL1 and the bit line pairs BL1P and BL2P. The bit line sense amplifiers 12-1 and 12-2 amplifies data of the bit line pairs BL1P and BL2P.
When a read command (not shown) and a column address CA is applied, the column decoder 18 generates the column selecting signal Y0 having a logic xe2x80x9chighxe2x80x9d level. So the data IO gates IOG1 and IOG2 are turned on to transfer data of the bit line pairs BL1P and BL2P to the local data IO line pairs LIO1P and LIO12P. The current sense amplifier load circuits 14-1 and 14-2 supply an electric current for the local data IO line pairs LIO1P and LIO2P and the data IO line pairs DIO1P and DIO2P. The current sense amplifiers 16-1 and 16-2 amplify a current difference between the data IO line pairs DIO1P and DIO2P to generate data D1 and D2.
In the semiconductor memory device of FIG. 1, data read from the memory cells MC1 and MC1B and MC2 and MC2B farthest from the current sense amplifiers 16-1 and 16-2 and differ in read speed the most from data read from the memory cells MC3 and MC3B and MC4 and MC4B nearest to the current sense amplifier 16-1 and 16-2. That is, a transmission speed of data read from the memory cells MC1 and MC1B and MC2 and MC2B farthest from the current sense amplifiers 16-1 and 16-2 is later than that of data read from the memory cells MC3 and MC3B and MC4 and MC4B nearest to the current sense amplifier 16-1 and 16-2. This is because a resistance value between the memory cells MC1 and MC1B and MC2 and MC2B and the current sense amplifiers 16-1 and 16-2 is larger than the memory cells MC3 and MC3B and MC4 and MC4B and the current sense amplifiers 16-1 and 16-2. This is due to the longer path.
FIG. 2 is a simplified circuit diagram illustrating a read operation modeling of the semiconductor memory device of FIG. 1. In FIG. 2, xe2x80x9cIcellxe2x80x9d denotes a memory cell current, and xe2x80x9cRloadxe2x80x9d denotes a resistor of a circuit that serves as a load during a data read operation, and xe2x80x9cVinxe2x80x9d denotes an input voltage of the current sense amplifier, and xe2x80x9cRinxe2x80x9d denotes an input impedance of the current sense amplifier, and xe2x80x9cIinxe2x80x9d denotes an input current of the current sense amplifier.
As seen in FIG. 2, during a data read operation, the memory cell current Icell dividedly flows to the load resistor Rload and the input impedance Rin of the current sense amplifier.
The input current Iin is described as the following equation:
Iin=Rload/(Rload+Rin)xc3x97Icellxe2x80x83xe2x80x83(Equation 1)
The input voltage is described as the following equation:
Vin=Iinxc3x97Rinxe2x80x83xe2x80x83(Equation 2)
If a resistance value of the input impedance Rin of the current sense amplifier becomes very small or xe2x80x9c0xe2x80x9d, all amount of the memory cell current Icell flows to the current sense amplifier. At this time, a resistance value of the input impedance, a voltage difference of the data IO line pair, becomes very small or xe2x80x9c0xe2x80x9d.
The resistance value of the input impedance Rin depends on a distance from the current sense amplifier to the memory cell. The larger the distance from the current sense amplifier to the memory cell becomes, the larger the resistance value of the input impedance Rin becomes.
Therefore, the farther the memory cell is from the current sense amplifier, the later a data read speed of the memory cell becomes.
FIG. 3 is a circuit diagram illustrating the current sense amplifier of FIG. 1. The current sense amplifier includes PMOS transistors P1 and P2 and NMOS transistors N7 to N9.
A resistance value for the input impedance of the circuit of FIG. 3 is obtained as follows. Note that xe2x80x9cIinxe2x80x9d denotes an input current that flows through the PMOS transistor P1, and xe2x80x9cVinxe2x80x9d denotes an input voltage, and xe2x80x9cgmpxe2x80x9d denotes a mutual conductance between the PMOS transistors P1 and P2, and xe2x80x9cgmnxe2x80x9d denotes a mutual conductance between the NMOS transistors N7 and N8.
The input current Iin is described as the following equation:
Iin=(Vinxe2x88x92Vout)xc3x97gmpxe2x80x83xe2x80x83(Equation 3)
The output voltage is described as the following equation:
Vout=xe2x88x921xc3x97(gmp/gmn)2xc3x97Iinxe2x80x83xe2x80x83(Equation 4)
Accordingly, a resistance value of the input impedance Rin is obtained by the following equation:
Rin=Vin/Iin=1/gmpxc3x97(1xe2x88x92(gmp/gmn)2)xe2x80x83xe2x80x83(Equation 5)
In Equation 5, xe2x80x9c(gmp/gmn)2xe2x80x9d denotes a loop gain T.
In the current sense amplifier of FIG. 3, the input impedance Rin between the data IO line pair DIO and DIOB can have a very small resistance value, due to potential positive feed back of the current sense amplifier.
As can be seen in Equation 5, if the loop gain T of the current sense amplifier is xe2x80x9c1xe2x80x9d, the input impedance Rin has a resistance value of xe2x80x9c0xe2x80x9d. As a result, the voltage difference between the data IO line pair DIO and DIOB becomes xe2x80x9c0xe2x80x9d, and the current sense amplifier amplifies a current difference between the data IO line pairs DIO and DIOB to generate the output voltage Vout. That is, the current sense amplifier operates ideally.
However, if the current sense amplifier is designed to have a loop gain T of more than xe2x80x9c1xe2x80x9d, the input impedance Rin comes to have a negative resistance value. This results in an unstable system, and the output voltage Vout oscillates.
Conventionally, the current sense amplifier of the semiconductor memory device is designed for its input impedance to have a very small value so that it can best accommodate reading the farthest memory cells.
However, even though designed for the impedance to have a very small value, the current sense amplifier cannot be designed for the loop gain T to have a value of more than xe2x80x9c1xe2x80x9d. That is, the current sense amplifier cannot be designed such that the mutual conductance gmp is larger than the mutual conductance gmn. Therefore, a problem exists, in that data of the memory cell farthest from the current sense amplifier are read with a delay.
Also, even though the current sense amplifier is designed for the loop gain T to have a value of less than xe2x80x9c1xe2x80x9d, the input impedance Rin can have a negative value due to variations in conditions. Such conditions include process conditions, voltage and temperature variations, operation variations, etc. In this case, the output voltage oscillates, preventing the generation of stable read data.
To overcome the problems described above, the present invention provides a semiconductor memory device that can improve a data read speed difference between the memory cells.
A device according to the invention includes a plurality of memory cells and a current sense amplifier. It also includes a feedback circuit to adjust a gain of the current sense amplifier. The gain is adjusted depending on relative delays of data stored in different ones of the memory cells to be read on the current sense amplifier.
The present invention further provides a data read method of a semiconductor memory device including a plurality of memory cells. The method includes generating a control signal to control a loop gain of a plurality of current sense amplifiers by detecting a variation of an input impedance of the current sense amplifier when a read command is applied and data are read from the memory cell nearest to the plurality of the current sense amplifiers; controlling the loop gain of the plurality of the current sense amplifiers in response to the control signal; and amplifying a current different of each of a plurality of data IO line pairs by the plurality of the current sense amplifiers to generate a plurality of output signals.
The semiconductor memory device according to the present invention can set the loop gain of the current sense amplifier to be more than xe2x80x9c1xe2x80x9d, and maintain the loop gain if the input impedance is positive. The semiconductor memory device can generate stable read data by reducing the loop gain when the data are read from the memory cells near to the current sense amplifier and when the input impedance becomes negative due to a process condition, voltage and temperature variation.
These and other features and advantages of the invention will be better understood from the following Detailed Description and attached Drawings, in which: